page created 2005-06-17 by Yann Guidon / whygee(a)f-cpu.org
Legend : (ok),
version française :
version: 2010-05-09 status:
Minor upgrade, link updates. Read the latest news on the blog.
The documentation is not yet completely updated but the code is working well enough
to justify a "green" status. The disassembler is re-enabled and the opcodes pass the autotest.
The extended instructions are not yet complete and call/jump instructions are missing.
So the "green status" means that the code is self-coherent, it is however incomplete.
The acronym "YASEP" means "Yet Another Small Embedded Processor".
It's a configurable (16-bit or 32-bit) microcontroller core that I have imagined,
in parallel (and sometimes in contradiction) with the F-CPU project.
It is meant to be small and as simple as possible (well, that's the original idea).
This allows me to develop it with limited efforts and reduced resources.
The trick is that by choosing sometimes unusual methods, it is
possible to concentrate on the real issues of CPU development
(mainly : architectural choices and implementation details).
The YASEP exists in the form of a package
that is not just a simulator, an assembler, a disassembler,
a manual, a development tool, it is all that and it will be much more !
Every part is integrated in the others (and vice versa),
so the whole remains (almost) coherent, easy to use and quick to develop, fix,
The only requirement is the use of Firefox,
see the browser compatibility list.
Happy clicking ! yg
The YASEP's features and characteristics :
Single-issue, pipelined, in-order, RISC architecture with 16 "registers"
Orthogonal 16-bit instructions : about 40 opcodes with
an optional 16-bit additional immediate word or extended mode
Compact instruction words with short and long immediate, 2, 3 or 4 register operands.
Adapted for memory-intensive applications with register-mapped memory :
an instruction can trigger up to 3 data memory accesses, instead of 1 for a
typical load-store architecture.
a direct integration of the programming tools.
The RTL source code is in VHDL (suitable for FPGA and ASIC). Actel's ProASIC3
is the targeted technology, other brands will come later.
The YASEP is Free Hardware ! It is available under the Affero GPL license.
No patent (pending or known) applies to this core.
All the code is original and copyrighted by myself (except a few places
that are specified otherwise), no licensing fee is collected. And your help is welcome :-)
The resources of this site/package :
The whole directory tree (about 340KB) is available for your
download/local/offline pleasure. You can test the YASEP at home, and play
with the source code at will. Note : if you want to use the file save/load features of FileFox,
you need a web server with PHP on your computer. Install Apache under GNU/Linux,
or EasyPHP under MS Windows.
The interactive opcode map of the YASEP.
You can reach a specific opcode from another page by clicking on this style of link : SHH.
The Interactive Assembler is a simple form
that lets you assemble single instructions.
It is also exported to other windows, so you can click on links like this :
add r0 d1. It also provides disassembly of single
opcodes : 5BA0590Dh(ok)
The description of an individual opcode (like "ADD")
can be accessed from many documents, for example by clicking on the corresponding
name in the interactive opcode map
or in the floating assembler window. (ok but more examples are needed)
This is the core of the project, but it is yet under-developped. YASEP16 gets the priority at this time of writing.
The source files are not up-to-date yet.
file that can be saved on your computer (for RTL simulation and synthesis).
The key parameters can be selected with a simple web/form interface. (ok) will be moved to listed too
This is where future functionalities are developped !
definitions and small utilities to make the simulator tick, without communication with any user interface.
in order to keep it separated from the real core files. This is were you'll find language and platform-dependent code,
as well as a few other cool JS hacks :
here is a demonstration of the functionalities.
The changes.txt keeps the track of the major changes applied to the files.
A HTML, CSS and JS minifier will be used for the entire site in the future.
These things are kept for historical purpose, eventually because no suitable replacement has
been written yet, or just because I don't want to erase them...
The original text-only draft of the (old) VSP.
Most details are outdated but it can give you an idea of how much it has evolved.
YASEP-related websites :
The YASEP has its own website : yasep.org. You are probably reading this there.
Some mirrors exist as well, and may be out of synch. The one at seul.org vanished in early 2010
due to technical problems, after 10 years of great service. Another mirror
is now available from TuxFamily. Thank you !
A blog provides less-technical informations and some human interaction.
Other sites (more or less related)
OpenCollector is the best place to look for other Free designs and tools !
OpenGraphics is designing a very nice
FPGA board that has a lot of potential
as a CPU development board. Buy one !
Yet another nice little FPGA board from Jopdesign
(JOP being a Java Optimised Processor released under GPLv3)
The Homebuilt CPUs WebRing is maintained by Dave R Brooks and dedicated to machines that
1. use a home-built CPU, not a bought one, and
2. have actually been built in hardware, not just simulated, etc.
Please keep in mind that this work is constantly in progress, the files change often and bugs appear and disappear without prior notice.
Check the changes.txt file for the latest changes, ongoing ideas, known bugs and missing features.
All these files are (C) Yann Guidon 2002-2010 and are provided for the visitor's fun under the Affero GPL License v3
These pages are barely W3C-compliant, I just want them to work under Firefox. I'm an electronician, not a web designer !
Thanks to all people who have helped (directly or indirectly) with code, comments and insight