The YASEP flavors
YASEP defines one architecture and instruction set with two similar subfamilies,
with a 16-bit or 32-bit wide datapath (YASEP16 and YASEP32 respectively).
They share about 90% of the behaviour and we try to keep as much features in common as possible.
We'll mainly speak about the differences here.
The first obvious difference is the word size : YASEP16
requires more instructions than YASEP32 to process 32-bit values, so it's adapted
for classic microcontroller uses, for example. YASEP32 is more
fluent when fast datastreams must be processed (the datapaths are larger
and the memory bandwidth is increased), it can handle some graphics or more sophisticated
protocols (like TCP/IP).
The second obvious difference is the silicon footprint : YASEP16
uses roughly half the logic gates of YASEP32. If a compact CPU core
is needed (for a small FPGA), YASEP16 will leave more room for
peripheral circuits. And YASEP16 runs maybe 15% faster thanks
to shorter logic critical datapaths and shorter wires (because of the smaller size).
A third difference deals with memory. The program memory footprint
is not much affected (the instructions are the same)
but YASEP16 can only access 64K bytes (it is more
adapted to short programs). An address extension mechanism (with a page
table) can be used to extend the total addressable memory,
and different threads can access different memory areas
(as well as share some) but a pointer is still limited to 64K.
YASEP32, with the recent changes in the architecture, can access a theoretic
4GB area per thread (though it is not planned to support or implement as much yet).
The fourth difference is in the instruction set.
Some instructions that deal specifically with words or half-word
make no sense with YASEP16, which uses the half-word (16-bit)
for everything. The instructions
are specific to YASEP32 and may trap (or hang the core) when executed with YASEP16.
To help prevent coding mistakes, the YASEP32
and YASEP16 pseudo-instructions have
been defined. They indicate to the assembler which YASEP "flavor" is targeted,
so it can issue warnings when an assembled instruction is invalid for the selected core.
Most other internal mechanisms are unchanged. For example, the Special Registers
have the same addresses (in the lower 64K range), so code can be easily ported.
The trap&interrupt mechanism (which is also accessed through the Special Registers)
has the same structure too.