The YASEP's Special Registers

The memory is dedicated to instructions and data. Configuration and Input/Output belong to a separate addressing space that enforces a strict ordering of the accesses and requires less bandwidth : this is the Special Registers space (SR). These registers are accessed only with the GET and PUT instructions.

The SR space can access a large number of small registers that are dedicated to Input/Output, configuration, Trap/Exception/Interrupt handling, memory mapping/protection, thread management... Some "core registers" are fixed, but optional or user-defined registers can be added or removed.

The SR map must be mostly compatible with both YASEP16 and YASEP32. YASEP32 could access 4 billion registers but it is easier to work with the first 64K registers because the Imm16 field can access them directly. So all the vital Special Registers are in the first 32K addresses, leaving 32K addresses for easy access to user-defined I/Os for example. Since YASEP32 can access more registers than YASEP16, these "upper registers" are undefined now.

The Special Register's width is the same as the datapath : YASEP16 accesses 16 bits per register, and YASEP32 can access 32 bits. However, to preserve compatibility, YASEP32 is encouraged to use only the lower 16 bits when it makes sense (like configuration bits). However a 32-bit access makes sense for a pointer, for example. When YASEP16 holds a value larger than 16 bits in a SR, the value is broken down into two consecutive SRs with the lower bits in the lower addresses. For example the value 0x12345678 is stored as 0x5678 in the SR, and 0x1234 at SR+1. YASEP32 will be able to avoid the 2nd address and access the whole register in one instruction.

Some Special Registers for the first YASEP implementations (they are all implementation dependent) :

That's all for now, stay tuned for more informations.