in another page. In the end, everything will be loaded in the main index.html page. search engine compliance goes to hell too. - in fact, most links should be converted to so the actual links can be modified in one place. The JavaScript that "patches" the code does the interim work. - the floating asm and the static page should be better separated. - changes to setTimeout calls JS and optimisation : - http://dev.opera.com/articles/view/efficient-javascript/?page=3 - create something that concatenates all the JS files (and strips spaces etc.) to reduce download activity and latency on yasep.org's server ==> make a script ? - make yasep's structures into an object ("CPU" ?) to reduce the nbr of global variables 2009-03-24 I just read http://www.gnu.org/philosophy/javascript-trap.html from /. and I'll apply the principles on the YASEP code, once FSF disambiguifies the recommendations. In the source files : /* @Copyright (C) 200x Yann Guidon @licensetype AGPLv3 @licenseURL http://yasep.org/license/agpl.txt */ In the compacted files : //@source: URL 2009-04-07 - replaced ADDS1/ADDS2/SUBS1/SUBS2 with COMPU/COMPS/SMIN/SMAX the functions are still missing and the VHDL does not have the signed overflow code. COMPU & COMPS pages of ISM must be written. - PC is now "Next PC" (NPC) because it's the most used data (PC remains available and gets copied to a SR when an instruction trap is triggered) -------------------------------------------------------------------------------------------- http://news.yasep.org/ what about YASEP2009 ? By whygee on Thursday 19 March 2009, 14:50 - Updates and news Development of and around YASEP is going on in a weird way, but it still continues... Why so much caution ? Because the changes to the architecture are quite deep. The instructions forms are increasingly complex and I've pushed the design beyond what I intended in the beginning. If you don't remember, YASEP had only two ways to address data previously : short form : Reg1 OP Reg2 => Reg1 (16 bits) long form : Reg1 OP Imm16 => Reg2 (32 bits) Now a few bits are freed and this gives much more "flexibility", so I added : Short Immediate : Reg1 OP Imm4 => Reg1 (16 bits) Long Register : Reg1 OP Reg2 => Reg3 (32 bits) And because there was still some room, this last form has more elaborate versions : Long conditional : Reg1 OP Reg2 IF{NOT} Reg4{LSB/MSB/Zero/ready} => Reg3 (32 bits) And other versions come up when the Reg2 field is interpreted as Imm4 : Long conditional short Imm: (excuse the name) Reg1 OP Imm4 IF{NOT} Reg4{LSB/MSB/Zero/ready} => Reg3 (32 bits) Or without condition : Reg1 OP Imm4 => Reg3 (32 bits) This applies to the computation instructions, the control instructions are still too undefined yet. Code density should increase, which is worth the efforts. I don't know if it will reach the level of ARM or x86 but it is certainly a major advance. However, this breaks a lot of the assembler's mechanisms, so I prefer to rewrite it. This takes a while because the rest must be adapted too : the Instruction Set, the manual pages, the validators... If you can't stand the wait, have a look at the current broken version at http://yasep.org/~whygee/yasep2009/, at least it is more recent than the main site. -------------------------------------------------------------------------------------------- Yet another Instruction Set Architecture change By whygee on Saturday 4 April 2009, 14:36 - Architecture I wish it could stabilize soon, but at least movement is a sign of activity (or the reverse :-)) I was annoyed by the ASU operations : ADD, SUB, ADDS1, SUBS1, ADDS2, SUBS2, MIN, MAX These instructions were the last ones that used skip technique, since it is progressively dropped in favor of relative branches by conditional add/sub to the PC register. How is it possible to provide the same functionality without skip ? It's the same old question that decades of research has not yet answered definitively. The Carry Flag is the obvious solution but I have just dropped the "status/mode register" in favor of another general purpose register. So where can I find a stupid bit of room ? The answer is there under my eyes : the LSB of the NPC ... OK OK I know it's ugly. But consider these aspects : * The PC points to the next instruction and never uses the LSB because all the YASEP instructions are aligned on 2-bytes boundaries. * Any write to the PC register modifies the bits 1 to 31. Bit 0 comes from the ASU's carry output. * We can declare that only the ASU operations (or context changes) can change the PC's LSB. All the other instructions can read it and test it, so the informations is easily available. * Since we dropped the 4 instructions that used skip, these "slots" can be filled by other instructions : CMPS, CMPU, SMIN, SMAX CMPx are just like SUB but don't write the result back. I wish it could set the LSB of any register but the current architecture doesn't allow this, so please keep the destination field to PC when encoding the assembly instruction. 3 new instructions deal with signed comparison : CMPS, SMIN & SMAX. They were missing from the previous opcode maps but the elimination of the skip-instructions leaves enough room. I have to update the VHDL now... * Keeping the carry bit in the LSB of the PC can have a curious side effect : relative jumps with odd values will make the carry bit ripple to the other bits of the result, so the destination address that is written in the PC will depend on the value of the carry bit. In practice, there is no speed or size advantage (compared to condition codes in the new opcode extension) but the possibility is there... * Clearing the carry flag is done with CMP Rx, Rx * Setting the carry flag is done with CMP -1, Rx (or something like that) Usually, I would end the post with something along the lines of "this is good and everybody is happy". Now, I feel a bit disapointed that YASEP looks more like other architectures, and has less distinguishing features. It is less groundbreaking and it will have to face the same problems as the others, on top of its inherent quirks. But it's still better than nothing and I do my best to keep the system rather coherent and orthogonal. -------------------------------------------------------------------------------------------- First details of the new "extended" long instruction By whygee on Saturday 4 April 2009, 16:31 - Architecture A precedent post has summarised the available "instruction forms", with or without immediate field (4 or 16-bits), with 2, 3 or 4 register addresses. Here we look at the "long form" (32-bit) using the "extended" fields that add 2 register addresses, conditional (speculative) execution and pointer updates. Let's now examine the structure of the 16 bits that are added to the basic instruction word : * One bit indicates if the source is Imm4 (it replaces the corresponding field in the basic instruction). * 2 bits indicate a condition (LSB, MSB, Zero, Always) * another bit negates the result (The condition "never" will be used later but I'm not sure how). * 4 bits indicate which register is being tested * 4 bits indicate the destination register (replacing the src/dest field in the basic instruction) * 2 fields of 2 bits each encode the auto-update functions of one source register and the destination register (nop, post-inc, post-dec, pre-dec) These fields are mostly orthogonal and can work in almost any combination. One can auto-update 2 registers (whether they are normal or belong to a memory access register pair), perform a 3-address operation and enable write-back depending on 97 conditions. It also preserves the availability of short immediate values, which further reduces code size. However it can increase the core's complexity. One unexpected bonus is that this new architecture iteration is more compiler-friendly. At least, it's much less awkward or embarassing. One bit could have been saved : the imm4 flag could be merged in the auto-update field for a source register. However this increases the logic overhead and prevents simultaneous use of auto-update AND imm4. Stay tuned... -------------------------------------------------------------------------------------------- 2009-05-26 - YASEP16 just got the register set and synthesises to > 90 MHz, enough for 12ns SRAMs. - moved MULxxx to a specific group (il will be merged later...) - distilled some of the newest changes in the core files : conditional stuff, extended forms... but still a lot of work to do. - constants : add alphanumeric/ASCII ? and explicit long/short specifier 2009-06-01 : - moved /test/ygwm, /test/minifier and /test/listed to / beware of symlinks because they don't get ported to windows - working on /filefox, data backup seems almost OK, I'm refining it now. it should get integrated in ygwm - trying to export the opcodes and instruction fields to VHDL 2009-07-06 - changed some CSS colors - created the /obsolete directory, moved old stuff there. - the documentation MUST be rewritten - TODO : ASCII text constants are still missing - pages à faire : registres, formats d'instructions (DONE) - some updates to /docs/assembly.html, not finished - moving ygwm and filefox to JSgui - moving listed to tools 2009-07-07 - /fr directory removed, Laura proposes to rename candidate files as *_fr- then _fr when finished. The translated files remain in the same directory to avoid breaking the links and paths. - "never" condition => call ? and what about the free source register read field ? 2009-07-09 - playing with JSgui/js_list.js * later, all the JS files will be minified into 1 file (the CSS too !) * tested/hacked files are renamed with a -2 suffix * prepare a way to have several message windows on screen => message_window object ? * remove JSgui/link_opcodes.js later as it is (conditionaly) integrated in page_pre.js * avoid the update of docs/assembly.html * FLAG_NOEXT => forme étendue impossible ou équivalente à forme courte ? * FLAG_SWAPDEST à revoir / refondre !!!!!!!!!! BIG MIX : SRC1 <> SRC2 fields are not coherent in the documentation !!!!!!!!!!! 2009-07-19 * At Laura's request, I'm adding aliases to the load/store instructions, so the semantic as insert & extract is clear. SB -> IB LZB -> EZB LSB -> ESB SH -> IH SHH -> IHH LZH -> EZH LSH -> ESH 2009-07-22 opcode flag ==> attribute ? 2009-07-23 columns can be hidden in listed TODO (DONE) : "objectify" the assembler, disassembler and CPU description. 2009-07-27 the assembler has been "object"ified and the constructor is Yasep_asm 2009-07-28 the whole CPU definition is objectified as "Y" TODO (DONE) : - The src1 and src2 fields are messed up all over the code, they must be checked carefully on the old gif, src1 is bits 12-15, but it's now bits 8-11 (exchanged with src2) but src2 is negated (it's src1 now) and src1 is mux'ed with Imm16 (src2 now) I don't know when/how the swap happened. VSP05.txt says "bits 8-11 : source/dest register number" so only the name, not the place, has changed. - then the flags (swap_dest for example) must be checked - then the disassembler can be restored - then the extended forms should be supported ygwm & the floating asm window can be disabled : write "disable_ygwm=true;" next to the definition of "prfx" this should shorten some page's loading^Wrendering time a little bit. and it's compatible with minification. 2009-07-29 : the forms with i are better supported TODO (size reduction of the archives) (DONE) : - convert from DOS format (remove one byte per line) - remove duplicate "version" words in headers note : now we have a 3-register form (RRR or RIR or RiR) so there is no need to overwrite the substractand (like with PICs) ==> SUB is now marked as SWAP_DEST (could also be done for ADD since it's a commutative operation) added new flags : ALIAS_RIR & IgnoreImmSign 2009-07-30 benches/test_opcodes.html : mauvaise gestion des alias => désactivée TODO : new core diagram that replaces docs/yasep_pipeline2007.gif (already replaced by yasep2009.gif) rename the ambiguous "src1" and "src2" with "si4" and "snd" created : docs/instructions.js renamed FLAG_ALIAS_RR to ALIAS_RR renamed FLAG_SWAPDEST to SWAPDEST updated ISM : ROL/ROR/UMIN/UMAX/SMIN/SMAX 2009-08-04 : @Vila ca \o/ * added flag NO_WRITEBACK * updated registers(_fr).html * READ_SRC1orIMM : removed it is implicit and always speculatively performed. so it's easier to define the reverse condition, when it appears. - IGNORE_SND - IGNORE_SI4 - ... ? * removed USE_IMM16 : redundancy with ALIAS_RR (NEG and NOT only) * READ_SRC1 is not used => removed * READ_SRC2 seems useless => removed * Y.WRITE_SRC1 removed , too... * JScore/group_eu2.js objectified and Y dropped 2009-08-08 Done : JScore/group_asu2.js is redesigned. * todo : add the "signed" input port to the VHDL code of ASU : this will enable/disable the input XOR of the 15th bit. cost : 2 AND2 gates ? * TODO (DONE) : aliases for the conditions : if_borrow if_carry if_no_borrow if_no_carry => substitution before the asm ? to be done (again) : (DONE) - the flags (swap_dest for example) must be checked - then the disassembler can be restored - then the extended forms should be supported 2009-08-09 group_shl : removed FLAG_SWP ready : SHL, ROP2, ASU, MUL must be updated : CTL, RSV, IE => IGNORE_SND, IGNORE_SI4 * TODO check that the fields are OK for IE, JS vs VHDL 2009-08-10 * rebuilding the disassembler. 0 error in the opcode autotest. * added Y.IGNORE_IMM16 (redundant with Y.FORMS_X ?) * F4 and F8 defined early in yasep_fields2.js so it's used mostly everywhere * removed SWAPDEST (only used by ADD/SUB...) * TODO : opcode fuzzer ? - ALIAS_RR == FORM_R ? - FORM_IR : what fields are really used ? * new flag SWAP_IR 2009-08-12 * starting the extended instructions * RiR => iRR (si4 first so "short forms" can be easily "promoted" as extended when a condition is specified) 2009-08-15 Win2K HD crash, several VHDL files are unavailable. * the tests must be updated to std_ulogic * operands DataA & DataB must be changed to SI4 & SND SHL, IE : ok ASU : changed DataA, DataB for SI4&SND, updated for signed comparisons : if (MulMux = '0') then ActualA := (SI4(15) xor signed_comparison) & SI4(14 downto 0); ActualB := (SND(15) xor (Addsub and (not signed_comparison))) & (SND(14 downto 0) xor (14 downto 0=>Addsub)); else ActualA := "0000" & AuxLo; ActualB := AuxHi & "0000"; end if; test_diff : in the test n°0, equivalence is OK when addsub <= AddSub and not (mulmux) signed_comparison <= signed_comparison and not (mulmux) (because some optimisations in the MUX break the thing otherwise) MUL8x4 : changed the polarity of WrEn and MulEn so they are active when 1 changed val to init MULI : found the algo for the initialisation of the LUTs : R1 : SND (first address + outer loop counter) R2 : SI4 (second address (lower byte) + init value (higher byte)) R3 : accumulator : second address increment + init increment (higher byte) R4 : inner loop counter A0 : inner loop address A1 : outer loop address mov 0 R1 mov 11h R3 mov 1 R4 mov NPC A1 ; outer loop 16 times : mov 0 R2 mov NPC A0 ; inner loop 16 times : ADD R3 R2 MULI R2 R1 ror 1 R4 mov A0 NPC LSB0 R4 add 100h R3 add 1011h R1 mov A1 npc no_carry ; the end ==> created docs/multiply.html * changed RIR to IRR everywhere * TODO : signed multiply * TODO (DONE) : revert the filenames back to without the 2 postfix in yasep/JScore * TODO : add another field in the LOAD instructions so unaligned accesses are possible in RRR form (one R holds the value of the precedent register) 2009-08-16 - starting to implement the conditional instructions. - swapped Y.FIELD_EXTSRC4 and Y.FIELD_EXTDST3 : EXTDST3 is now 16 bits away from SND, EXTSRC4 is 16 bits away from SI4. This should spare a MUX or two in the decoder. * TODO : docs/assembly_fr.html must be translated (only started, quickly stalled) - created JScore/yasep_conditions.js * IDEA : the condition codes do not use the src4 fields for the ALWAYS and NEVER codes. => ALWAYS is condition 0 with src4=0. The rest could be used ... src4 could select one bit amond 15 (bit#0 is stuck to 1) the bit could come from either I/O pins or a register (SR ? what about context change ?) 5 conditions could be used later, linked to the 5 memory register pairs, so specific code can be executed when the memory is not ready, or if the value has been changed/altered by another thread (for example). * TODO : align pseudo-opcode ? * TODO (DONE) : exchange SI4 & SND, or DST3&SRC4 again ?? (it seems that I made a mistake earlier) 2009-08-17 - the instruction form examples are now random. They change at every page reload. it's one first step towards a fuzzer... TODO : the instruction decoder should be better factored 2009-08-18 - dans le bus de retour de Vila Ca pour l'opcode-autotest, les instructions qui ne passent pas sont : - LZH, LZB, LSH, LSB : RRX ==> décode comme RR ?? - INV, CRIT et HALT : * FORM_ALONE conditionnel => décodage marche pas * FORM_X décodé comme IRR idée : éliminer les FORM_X et encoder des formes étendues à la place. ça élimine tous les FORM_X et on met "always" comme condition à la place. par contre c'est pas réversible donc l'autotest marchera pas, il pourra pas savoir si un "always" a été mis puisqu'il est par défaut... 2009-08-23 De toute façon, les formes "X" sont chiantes et inutiles, pas la peine d'encombrer le désassembleur et l'opcode map avec ça. reste aussi à remettre les champs SRC4 et DST3 correctement. TODO : fenêtre de messages avec boutons pour accepter les messages d'erreur/warning/etc. le désassembleur est quand même dans un sale état. --- idea : use the 0xA0 bytes in the JS strings that contain contiguous spaces to avoid removal of spaces during minification. => The french pages won't allow this because of the encoding, so I have to change the encoding. 2009-08-24 * TODO : abstract/vendor independent versions of the units => VHDL Versions of the arrays * TODO : ABS alias ABS R1 => SUB 0 R1 R1 MSB1 R1 ABS R1 R2 => SUB 0 R1 R2 MSB1 R1 ==> signed multiply : - need another tmp reg (stack ?) xor R1,R2,t abs R1 abs R2 (mul16) return si MSB0 t neg Res return soucis : comment ajuster la sortie sans faire de ABS en entrée ? comment faire le NEG d'une paire de registres ? comment faire cela pour toutes les tailles et combinaisons avec immédiats ? neg 32 bits avec op 16 bits : neg Rlow and 1 PC Rt sub rt, Rh, rh 2009-08-29 Multiply : available in 2 versions (when available) * When the LUT method is used, 3 instructions are provided : MUL8L, MUL8H, MULI * When a HW multiplier is available, these instructions are implemented : UM16H, UM16L, SM16H, SM16L These methods exclude each other, so they share the same 4 opcode values. The sharing is managed with aliases. A JS flag in the CPU object will determine which opcode to use. The 4 following opcodes are reserved for division. 2009-08-30 * adding the new "YASEP configuration panel" as a floating window -> There are now 2 kinds of properties : "build" and "runtime" for multiply, datapath size etc. * "build time" properties are used for VHDL generation * "buildtimes" are copied to "runtime", which can be changed during assembly * the floating asm window's contents is now generated after load time, so the red message does not appear/flash anymore when a page is loaded. I use the new DOM method for the confpanel as well, and the other/next windows will do too. * instructions that read and write to another register bank/thread ? * onchip memories for FPGA made with BlockRAM ? => make parameterised VHDL that takes a certain amount of block RAMs and assembles them into a larger memory array. - They won't be very "large" (some KBs) so no need of remapping blocks. - dual port is possible so simultaneous instruction+data is possible => pipeline faster - wide datapaths make buffering/caching possible => preparation of newer architectures => A3P125/A3P250/AFS250 : 2 for R7, 2 for MUL, 4 remain for SRAM => 2KB of SRAM A3P400 : 4KB A3P600, AFS600 : 8K A3P1000 : about 15K AFS1500 : about 30KB ! * IDEA : addresses FFF8 to FFFF are reserved as scratch pads. they can be used when a D register serves as a R register, so A0=0, A1=1, etc. in fact, it uses the sign extension of the constant field to avoid overwriting the boot code at address 0 : A1=-1, A2=-2, A3=-3, A4=-4 => this fits into short instructions warning : when possible, use the thread's stack to avoid concurrency issues, and beware of address remappings and threads... this makes a long instruction : ADD -1, Astack, A1 ADD -2, Astack, A2 ADD -3, Astack, A3 ADD -4, Astack, A4 => Astack=A0 ? 2009-09-02 : * TODO : s/YASEP/the YASEP/ , s/YASEP/le YASEP/ 2009-09-20 : - TODO : s/SULV/SLV/ in VHDL and generator code - Problem : the GET/PUT will take a LOT of time, several cycles, maybe even a variable time :-( idea : GET/PUT behaviour : blocking access when index is negative ? bad because the behaviour is not known at opcode decode time, but at read time stall signal is necessary :-/ write instruction will not stall because it's the read that takes time with the big MUX/AOx 2009-11-6 * slashdot.org linked to http://closure-compiler.appspot.com/home and I'm playing a bit to see how to make my code better. - 'const' are not allowed ? o_O - ygwm seems to have a duplicate ev function parameter in .hook() => fixed // ==ClosureCompiler== // @compilation_level SIMPLE_OPTIMIZATIONS // @code_url http://yasep.org/JSgui/page_pre.js // @code_url http://yasep.org/JSgui/filefox.js // @code_url http://yasep.org/JSgui/floating_asm.js // @code_url http://yasep.org/JSgui/yasep_messages.js // @code_url http://yasep.org/JSgui/ygwm.js // ==/ClosureCompiler== So it's good to spot otherwise uncaught JS troubles but closure-compiler will not replace my custom scripts because - it requires internet access - usage is limited - CSS & HTML are not processed - google's policy is not certain for the long term - one can't use the compiler on his own computer - the scripts already provide 80% of the compiler's gains with minimum efforts so closure appears as overkill 2009-11-11 I just discovered http://www.dinceraydin.com/lcd/index.html from wikipedia, and particularly the simulator : http://www.dinceraydin.com/djlcdsim/djlcdsim.html and I wonder how it could be integrated or linked with the YASEP simulator. Trying to contact the author, who has even made a JS PIC ASM :-D http://www.dinceraydin.com/pic/djpasm/djpasm.html Also interesting : http://home.iae.nl/users/pouweha/lcd/lcd0.shtml http://www.8052.com/tutlcd2.php 2009-12-01 /. : http://wiki.commonjs.org/wiki/CommonJS Also : the main clock is now defined as 3.6864MHz so the clock consumes less than a canned oscillator at 25MHz. RS232 : the baud rate is a simple division by 2 1843200 921600 460800 \ 230400 - OK for USB/Linux communication 115200 / 57600 28800 When divided by 3, it generates 1.2288MHz : 614400 307200 153600 76800 38400 \ 19200 \ standard rates 9600 / 4800 / So a 10-bit baud ratio register is enough. RTC : divide by 225 (5*5*3*3) and get 16384KHz => a 14-bit counter gives a direct reading of the current second's time => A 14-bit "mask" register can trigger a thread to pop up every 2^-n second. => This could also trigger A/D conversions of accelerometers Sound : multiply by 10 and divide by 3 : 3.6864 * 10 / 3 = 12.288MHz => 48KHz * 256 or multiply by 5 : 18.432MHz => 48KHz*384 (another common ratio) 44100Hz (2*2*3*3*5*5*7*7) is too complex to get. CPU : the PLL can be started with a low multiplier that is then dynamically tuned to match the SRAM's speed and/or workload. The RTC will still trigger the events based on the second, not the CPU's clock counts. With a 3.6864MHz base clock, the CPU speed can be finely adapted, from this up to about 100MHz with tens of intermediary steps ! Pour la calibration : 1 source 1Hz, 1 timer 24 bits et 1 sortie sur LCD pour le nb d'impulsions par seconde. * émulateur "microterminal" pour LCD ? dTCXO : - capteur température SPI ? - source 1Hz (GPS) - sortie DAC ? - 1 "timer" 32 bits avec entrée sélectionnable, + registre auxiliaire 10MHz = 2^7 * 5^7 3.6864 = 2^14 * 3^2 * 5^2 5^5 \ * 2^7 * 5^2 2^7 * 3^2 / 2010-01-17 * Oscillator is mostly OK, though not yet functional. I have 18.432 and 3.6864MHz crystals in store with most of the supporting parts. * TODO : support GHDL * TODO : create 2 VHDL packages so wires types can be SUL or bit, buses can be SULV or bit_vector => speedup of GHDL simulation ==> define YASEP_BIT, YASEP_VECTOR and conversion functions 2010-01-18 * TODO : compatibility.html : list the browsers that work and the known display bugs 2010-02-12 * discovered the HTML5 'canvas' and screenshot capabilities this is going to be a great tool for display emulation for the simulator :-) 2010-02-21 * added some alphanumeric LCD stuff, mainly a character editor and character bitmap table. /test/ is a real mess (I have added a lot of random stuff found on the 'net) so I'm not releasing anything yet. * TODO : finish the configurator at tools/generate_VHDL.html and integrate it in listed 2010-03-11 * TODO : add a new pseudo-instruction "assert" (reg/mem/sr) = (reg/mem/imm/sr) * TODO : changer SLV en ... ? YV : YASEP Vector ? 2010-03-17 -FORM_IR MOV 3587 R0 113: OK: opcode=MOV form=FORM_IR 4 bytes mask=FFFFF0FFh 114: OK: opcode=MOV instruction="NOP" (FORM_ALONE) 115: output != input * TODO : configurer la carte de la memoire, nb de bits d'adresse * fumble avec les encodages (UTF-8) sous fedora et noms de fichiers en minuscules :-( * miror @ tuxfamily.org new directory : logo contains http://faq.tuxfamily.org/images/Btn_tf2.png * TODO : code for bitcount with the MUL instructions and LUT ? problem : the adds are shifted * TODO : in Listed : add a search window, to locate occurences of a word in the edited source code * TODO : separate DATA and INSTRUCTION RAM spaces to accelerate the instructions fetch and reduce the memory bottleneck. * TODO : port VHDL-POSIX to GHDL 2010-04-19 * TODO : bridge from SR to Wishbone and other I/O buses