YASEP's interactive opcode map

This page is automagically generated by some Javascript code, based on the definitions found in the files of the JScore directory.

The opcodes

Unless otherwise noted in the flags, these opcodes support these 4 forms :
* short register (RR)
* short immediate (4-bit iR)
* Long immediate (16-bit IRR)
* Extended register (RRR) with conditional (RRRRc) and increment features.

Look at instructions.html for a detailed description of the instruction word's structure.

Opcode aliases :

Form usage by opcode :

The instruction's "form" reflects the semantics of the instruction. It is the assembler's view of the encoding.

Flag usage by opcode :

The flags contain the informations used by the assembler to transform the semantic into an encoded binary word.