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Missing : conditional instructions and pointer updates
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YASEP uses a 16-bit fixed-format instruction word with an optional 16-bit immediate field or a 16-bit extended word. This instruction format is identical for both YASEP16 and YASEP32.
Each instruction can contain :
These fields and flags are not all used at the same time. Some combinations are impossible by construction, some others don't make sense, others can be hidden by the assembler. However, a wide variety of instructions (an opcode followed by register names, immediate data or other flags) can be written by the user. This page explains what are the "instruction forms", how they are designed and when they are used.
An "instruction form" is named after the way it is written in assembly language. It is a sequence of letters that describe each used field :
The YASEP allows only a limited number of forms. The two least significant bits of each instruction determine how to interpret the operands and other fields. The 2 bits create 4 combinations :
The YASEP instructions write the result of an operation (when any) to a register whose address is given by the si4, snd or dst3 fields, depending on the instruction form :
It is justified to say that it is a bit complex and may make architectural development difficult in the far future. However, this is required to keep the instructions compact. Furthermore, in the datapath, what really counts is the access time of the operands, not the destination address which can be computed at the same time as the ALU (a good dozen of logic levels)
Let's start with the most simple instruction forms. The short instructions have their LSB cleared and are 16-bit long. This is enough for another flag, a 6-bit opcode and two 4-bit fields.
In practice, these 2 combinations can be used in 5 ways in assembly language, since any of these fields can be more or less useful depending on the kind of operation :
Form "RR" : Register to Register
ADD R1 R2 ; R2 <- R1+R2This is the most common form, where si4 and snd are both register operands, and the result goes to snd.
Form "iR" : short immediate to Register
ADD 2 R3 ; R3 <- 2+R3Another common form where si4 is used as an immediate value, so snd is used as both source and operand.
Form "R" : Register
NEG R1 ; internally : R1 <- 0 - R1It's also a short way to write that both si4 and si4 fields contain the same register address. The assembler will correctly fill the operand fields if the form is correct for the opcode.
Form "i" : short Immediate
CRIT 3 ; disable the interrupts during the 3 following instructionsNot used very often but sometimes necessary. si4 is used as an immediate value and snd is ignored.
Form "ALONE" : no operand
NOP ; Nop operand needed, all fields ignored.This is an extreme case where no operand is needed : si4 and snd are ignored.
YASEP interprets the instruction as 32-bit long when the LSB is set to 1. The 16 lower bits are exactly the same as the short forms. The second LSB selects how to interpret the higher half-word :
Form "IRR" : long Immediate and Register to Register
ADD 1234h R2 R1 ; R1 <- 1234h + R2This is another common form where the operands are snd (a register field) and the 16-bit immediate field. The destination register is given by si4.
Form "IR" : long Immediate to Register
GET 1234h R1 ; R1 <- SR[1234h]This form is used for the GET or MOV instructions. si4 is ignored because only snd makes sense for the operation. The assembler also detects when the immediate address is larger than 4 bits and issues a long or a short form.
This is also used (in conjunction with the ALIAS_IRR flag) by the ROP2 group and the ADD/SUB instructions : this is similar to FORM_iR but with a 16-bit immediate operand. si4 and snd have the same value.
Form "RI" : Register to Immediate
PUT R1 1234h ; SR[1234h] <- R1This form is currently only used for the PUT instruction. It is the same as FORM_IR but the order of the operands is reversed at the assembly language level to obey the rule #1 : "the destination is written at the end of the instruction".
The extended forms reuse the short form's structure and add 16 bits for several additional features :
Form "RRR" : Register and Register to Register
ADD R1 R2 R3 ; R3 <- R1+R2si4 (R1) and snd (R2) are both register operands, and the result goes to dst3 (R3).
Form "iRR" : imm4 and Register to Register
ADD 5 R1 R3 ; R3 <- R1+5The 4-bit immediate field si4 (5) and snd (R1) are the two operands, and the result goes to dst3 (R3).