SH : Store Half-word (and update the pointer)

This instruction inserts one half-word (16 bits) in a given register, emulating the "Store Half-word" instruction of Load-Store architectures. The source data is shifted left, according to an offset, and inserted in the half-word pointed to by the offset in the destination register.

If the target register is a static register, then the offset is zero. If this is the Data register of a PFQ, the 2 LSBs of the associated pointer are used as offset, and the pointer is updated.

Because this instruction can't go beyond a word boundary, only offsets 0, 1 and 2 are valid. Attempts to use an offset of 3 triggers an alignment trap.