This instruction extracts one half-word (16 bits) from a given register, emulating the "Load Halfword" instruction of Load-Store architectures. The data is shifted right, according to an offset, and the MSB are filled with the sign bit of the extracted data.
If the target register is a static register, then the offset is zero. If this is the Data register of a PFQ, the 2 LSBs of the associated pointer are used as offset, and the pointer is updated.
Because this instruction can't go beyond a word boundary, only offsets 0, 1 and 2 are valid. Attempts to use an offset of 3 triggers an alignment trap.
For more background information, read the main VSP document.
- FORM_RR LSH R1 R2 - FORM_RRX LSH R2 R1 ?
opcode : LSH opcode number : 6Ah group : IE Description : Load and Sign-extend Half-word Forms : RR,RRX Flags : READ_SRC2 WRITE_SRC1
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