The microYASEP architecture

Overview

The miniYASEP is a subset of the YASEP family that targets microcontroller applications. It is more efficient than the microYASEP but uses more logic gates. It should still fit in small FPGAs and can be used when the microYASEP is performance-bound, above 20 MIPS. It preserves many of its main features but the scheduling is tighter, faster and more flexible, using a higher speed clock.

• Designed for the ProASIC3 (Actel/Microsemi) with LUT3 gates and scarce dual-ported SRAM blocks.
• Same configurability as the microYASEP : can work with 16-bits and 32-bits datapaths, configurable PC length, works with no, or very little, data memory...
• Higher performance (20 to 30 MIPS on PA3)
• Support for register post-increment : higher code density
• Support for on-chip debug

A variable-length, multi-cycle datapath is more efficient at hiding some latencies that are inherent in the microYASEP. The register set can be accessed more often for reads and writes so up to 4 registers can be read and written during one instruction, not even counting the 3 data memory accesses.