This instruction is part of the trio (with IPC and IPR) designed to provide safe calls between processes, almost as fast as function calls and without requiring microde.
The IPE instruction marks the entry point of a callable process and performs some security checks. It must be preceded by a NOP to resynchronise the instruction flow, ensuring that the the caller jumps to a real IPE instruction and not the end of a long or extended instruction. For example, the second half-word of the instruction ADD R1 R1 R3 BIT1 2 could be decoded as IPE R2 R3.
IPE performs some security checks and extra electronics ensure that the IPC-NOP-IPE sequence is atomic and enforced. If IPE is not preceded by a NOP, or if this NOP is not jumped to from an IPC instruction, a trap/exception is raised. The trap is also triggered if the IPC jumps to another instruction than NOP, or this NOP is followed by an opcode different from IPE.
IPE is not interruptible or predicable (still for security reasons) and it writes the ID of the calling process to the destination register, so the calls can be filtered in software.