Please read this page from the main YASEP interface
Configure the core NewProfile

This page generates a configuration file for the VHDL code. The rest of the VHDL code is in its own directory.

The configuration and options of a particular YASEP implementation are collected and stored in a "profile". You can edit and save it, after you import one of these existing profiles:

Profile name:
Program Counter width: bits

Datapath width:
16 bits
32 bits
Multiplier:
none
8×8 bits
16×16 bits
Condition as
a bit of R1:
disabled
enabled
Register
parking:
disabled
enabled
Opcodes: