-- test_IE_16.vhd

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.ALL;


entity test_IE_16 is
  generic (
    YASEP_SIZE : integer := 16 -- must be 16
  );
end test_IE_16;

-----------------------------------------------------------------

architecture bench of test_IE_16 is

  signal DataA, DataB : std_logic_vector(YASEP_SIZE-1 downto 0);
  signal Load, SignExt, OffsetA : std_logic;
  signal ResultIE : std_logic_vector(YASEP_SIZE-1 downto 0);

begin

  assert (YASEP_SIZE=16)
    report "YASEP_SIZE must be 16"
    severity failure;

  DUT:
    entity work.IE_16(second)
    generic map(
      YASEP_SIZE => YASEP_SIZE
    )
    port map(
      DataA    => DataA,
      DataB    => DataB,
      Load     => Load,
      SignExt  => SignExt,
      OffsetA  => OffsetA,

      ResultIE => ResultIE
    );

  process
    variable l: line;

    procedure run1(rot, dir, arith : std_logic; s: string) is
    begin
      Load <= rot;
      SignExt <= dir;
      OffsetA <= arith;
      wait for 10 ns;
      write(l,s);
      write(l,ResultIE);
      writeline(output,l);
    end run1;

    procedure run1x8(data : std_logic_vector(YASEP_SIZE-1 downto 0)) is
    begin
      write(l,string'("****************************************"));
      writeline(output,l);
      write(l,string'("dataA="));
      write(l,data);
      writeline(output,l);
      DataA <= data;
      run1('0', '0', '0',string'("MOVB  "));
      run1('0', '0', '1',string'("MOVA  "));
      run1('0', '1', '0',string'("SB0     "));
      run1('0', '1', '1',string'("SB1     "));
      run1('1', '0', '0',string'("LZB0   "));
      run1('1', '0', '1',string'("LZB1   "));
      run1('1', '1', '0',string'("LSB0   "));
      run1('1', '1', '1',string'("LSB1   "));
    end run1x8;

  begin

    DataB <= "00U00000111X1111";
    run1x8("0000000000000000");
    run1x8("1111111111111111");
    run1x8("1000000000000000");
    run1x8("0111111111111111");
    run1x8("0000000000000001");
    run1x8("1111111111111110");
    run1x8("0011110000111100");
    run1x8("1100001111000011");

    DataB <= "1U111111000000X0";
    run1x8("Z00000000000000Z");
    run1x8("Z11111111111111Z");
    run1x8("Z00000000000000Z");
    run1x8("Z01111111111111Z");
    run1x8("Z00000000000001Z");
    run1x8("Z11111111111110Z");
    run1x8("Z01111000011110Z");
    run1x8("Z10000111100001Z");

    assert (false)
      report "simulation finished OK"
      severity failure;

  end process;

end bench;