page created 2005-06-17 by Yann Guidon / whygee(a)f-cpu.org Legend : (ok), (warning), (bork)

version française :

version: 2009-08-23
status: The documentation is not yet completely updated but the code is working well enough to justify a "green" status. The disassembler is re-enabled and the opcodes pass the autotest. The extended instructions are not yet complete and call/jump instructions are missing.

Welcome to the YASEP project page

    YASEP means "Yet Another Small Embedded Processor". It's a configurable (16-bit or 32-bit) microcontroller core that I have imagined, in parallel (and sometimes in contradiction) with the F-CPU project.
    It is meant to be small and as simple as possible (well, that's the original idea). This allows me to develop it with limited efforts and reduced resources. Other people (students, hobbyists) can also easily participate and learn from this project. The trick is that by choosing sometimes unusual methods, it is possible to concentrate on the real issues of CPU development (mainly : architectural choices and implementation details).
    YASEP exists in the form of a package that is not just a simulator, an assembler, a disassembler, a manual, a development tool, it is all that and it will be much more ! Every part is integrated in the others (and vice versa), so the whole remains (almost) coherent, easy to use and quick to develop, fix, maintain... The only requirement is the use of Firefox (or any other Gecko-based browser) : this all-in-one project heavily relies on Mozilla's JavaScript engine. Opera and others seem compatible but actively supporting IE would be counter-productive.

Happy clicking !
yg

YASEP features and characteristics :

• Single-issue, pipelined, in-order, RISC architecture with 16 "registers"
• Orthogonal 16-bit instructions : about 40 opcodes with an optional 16-bit additional immediate word or extended mode
• Compact instruction words with short and long immediate, 2, 3 or 4 register operands.
• Configurable with either a 16 or 32-bit wide datapath with/without several features (memory, multiply...).
• Adapted for memory-intensive applications with register-mapped memory : an instruction can trigger up to 3 data memory accesses, instead of 1 for a typical load-store architecture.
• The high-level architecture is specified with JavaScript+HTML, with a direct integration of the programming tools.
• The RTL source code is in VHDL (suitable for FPGA and ASIC). Actel's ProASIC3 is the targeted technology, other brands will come later.
• YASEP is Free Hardware ! No patent (pending or known) applies to this core. All the code is original and copyrighted by myself, no licensing fee is collected. And your help is welcome :-)

The resources of this site/package :

Download

• The whole directory tree (about 340KB) is available for your download/local/offline pleasure. You can test the YASEP at home, and play with the source code at will.
  Note : if you want to use the file save/load features of FileFox, you need a web server with PHP on your computer. Install Apache under GNU/Linux, or EasyPHP under MS Windows.

Description, documentation and references (/docs directory)

• The description of the registers. [fr] (ok)
• The instructions, their structure, the forms and their syntax. [fr] (ok)
• The assembly language manual explains how to write YASEP instructions for the JavaScript assembler. (ok)
• The differences between YASEP16 and YASEP32 (the 16-bit and 32-bit datapath versions) [fr] (ok)
• How to use the multiply instructions (ok)
• The opcode flags (ok)
• The Special Registers have their own page, with a list of the addresses, values and functions accross 16- and 32-bit version. (not very useful yet)
• (Look at the Obsolete section for the old incarnations of the manual, before the instruction set and the registers were deeply modified.)

Software development and design tools

• The interactive opcode map of the YASEP. [fr] (ok)
  You can reach a specific opcode from another page by clicking on this style of link : SHH.
• The Interactive Assembler is a simple form that lets you assemble single instructions. It is also exported to other windows, so you can click on links like this : add r0 d1. It also provides disassembly of single opcodes : 5BA0590Dh (ok)
• The assembler will get a new fancy dynamic editor using ygwm. (preliminary)

The pages of the Instruction Set Manual of the YASEP (/ISM directory)

The description of an individual opcode (like "ADD") can be accessed from many documents, for example by clicking on the corresponding name in the interactive opcode map or in the floating assembler window. (ok but more examples would be great)

Testbenches and verification (/benches directory)

• The Opcode autotest is now available. This page exercises the disassembler with the assembler's output, seeking inconsistencies. (ok)
• The Execution Units can be manually exercised for the YASEP16 and YASEP32 versions. (ok)
  

RTL source code (/VHDL directory)

This is the core of the project, but it is yet under-developped.
YASEP16 gets the priority at this time of writing. The source files are not up-to-date yet.

• This page exports the JavaScript definitions of YASEP to a VHDL file that can be saved on your computer (for RTL simulation and synthesis). The key parameters can be selected with a simple web/form interface. (ok)

Various early clickodromes, prototypes and sandboxes (/test directory)

This is where future functionalities are developped ! Among others :

• An early GUI prototype of GNL (a graph-based programming tool), named ploped. (highly preliminary, probably broken and incomplete)
• I also started a JavaScript to C translator (highly preliminary, and not working good enough)

Others

• The /JScore directory contains JavaScript files for the YASEP core, like all the assembly, definitions and small utilities to make the simulator tick, without communication with any user interface.
  
• The /JSgui directory contains JavaScript files for the Graphical User Interface in order to keep it separated from the real core files. This is were you'll find language and platform-dependent code, as well as a few other cool JS hacks :
  • This project uses an original way to save or load file from/to JavaScript, here is a demonstration of the functionalities.
  • A specific JavaScript window manager has also been developped (early 2009).
• The changes.txt keeps the track of the major changes applied to the files.
• A HTML, CSS and JS minifier will be used for the entire site in the future.

Obsolete

These things are kept for historical purpose, eventually because no suitable replacement has been written yet, or just because I don't want to erase them...

• The original introduction to the YASEP can still be read. It contains most old rationales for the design, and a description of the core's architecture. (must be updated or partly rewritten)
  
• If you want to develop sofware with YASEP, you'll want to read the instruction set overview too. Well, the most recent one is more functional... (must be updated)
  
• The old pipeline simulator is still available, but obsolete, incomplete and useless (but funny and not lethal).
• The original text-only draft of the (old) VSP.
  Most details are outdated but it can give you an idea of how much it has evolved.

YASEP websites :

• The YASEP has its own website : yasep.org. You are probably reading this there, but some mirrors exist (like at seul.org) or might appear.
• A blog provides less-technical informations and feedback.

Other sites (more or less related)

• OpenCollector is the best place to look for other Free designs and tools !
• F-CPU is where it all started (more or less)
• Ours Agile is a robotic project that will use YASEP
• Jan Gray's fpgacpu.org is another inspirational site.
• The Harp Project is another attempt by a single person to design a CPU.
• Wikipedia has a realistic list of soft cores.
• ACME Systems SRL is the maker of the FOX VHDL board (now replaced by the COLIBRI board), equiped with an Actel ProASIC3 FPGA and a pair of high-speed SRAM. These boards are cheap and ideal for YASEP !
• OpenGraphics is designing a very nice FPGA board that has a lot of potential as a CPU development board. Buy one !
• Yet another nice little FPGA board from Jopdesign (JOP being a Java Optimised Processor released under GPLv3)